1. Field of the Invention
The present invention relates to ADC, and more particularly, to ADC timing and gain mismatch correction.
2. Description of the Prior Art
The analog-to-digital converter (ADC) is a common circuit component utilized in various applications. Time-interleaved parallel ADCs are commonly used, since the time-interleaved parallel architecture is attractive for implementing an ADC with a high sampling rate. Please refer to FIG. 1, which depicts a block diagram of a prior art M-fold time-interleaved parallel ADC module 340, where M is an integer greater than 1. Assume the target sampling rate is f. Using M-fold time-interleaved parallel architecture, one operates each of the M ADC's 342, 344, . . . , 346 at a sampling rate of f/M. Each of the ADC's 342, 344, . . . , 346 operates at the same sampling frequency of f/M, but at a respective, different phase. The phases of the ADC's 342, 344, . . . , 346 must be evenly spaced so as to occupy (i.e., cover) the entire sampling clock period, which is the reciprocal of the frequency f/M. As shown in FIG. 1, each ADC, beginning with ADC 342 (i.e., the first ADC) and through ADC 346 (i.e., the last ADC), uses a respective sampling clock. The clocks are labeled CLK_0 through CLK_M−1, corresponding to the respective clock for ADC's 342 through 346 The output from the M ADCs (342, 344, . . . , 346) are provided to a subsequent de-interleaver 348 to construct a digital output for ADC 340. The de-interleaver 348 is operated using clock CLK, which has a frequency that is M-fold higher than each of the sampling clocks CLK_0 through CLK_M−1.
Please refer to FIG. 2, which shows an example timing diagram illustrating clocks utilized by the M-fold time-interleaved parallel ADC module 340 shown in FIG. 1 for the example case of M=4. As shown in FIG. 2, the frequency of the clock signal CLK is four times of each of those of the clock signals CLK_0–CLK_3. Therefore, the de-interleaver 348 de-interleaves the outputs sequentially generated from the parallel ADC's 342 through 346 to form the desired digital output at a sampling rate of f.
However, in practical applications, the time-interleaved parallel ADC module 340 suffers from two problems. The first problem is called timing skew. To explain timing skew, consider a four-fold parallel architecture as an example. A four-fold time-interleaved parallel ADC module requires four individual clocks, each operating at the same frequency of f/4 but at a different phase. For example, one would like to operate the four clocks at phases of 0, 90, 180, and 270 degrees, respectively. In practical applications, such ideal results are not possible. In real-world applications, the actual clock phases might be, for example, 5, 85, 185, and 265 degrees. These actual clock phases are examples meant to illustrate that the actual clock phase very often differs by several degrees from its ideal phase. The imperfectly timed clocks can result from a number of factors; one for example, is due to the nature of the manufacturing process of the transistors and other circuit components of the clock source. Unfortunately, timing skew degrades the ADC's performance.
Additionally, the time-interleaved parallel ADC suffers from a second problem called amplitude (i.e., gain) mismatch. Amplitude mismatch of the M parallel paths is due to the limited component tolerance and imperfections in the manufacturing process of the circuit elements, i.e., ADC's 342 through 346. Amplitude mismatch will also degrade the ADC's performance.
The following U.S. Patents, for example, are all prior art attempts of mismatch correction schemes: U.S. Pat. No. 6,570,410; U.S. Pat. No. 6,522,282; U.S. Pat. No. 6,476,754; U.S. Pat. No. 6,407,687; U.S. Pat. No. 6,384,756.
However, prior art techniques attempt to solve the mismatch problems by regarding the ADC to be the target device under test. Prior art correction schemes inject a pre-known calibration signal at the ADC input and then estimate the mismatch based on the ADC's output. Alternatively, prior art correction schemes may also simply use the unknown analog input under normal operations and estimate the mismatch based on the statistics of the ADC output. These techniques for correcting timing skew and amplitude mismatch in a time-interleaved parallel ADC do not consider the overall performance of an application that utilizes the time-interleaved parallel ADC. For instance, if the time-interleaved parallel ADC to be calibrated is applied in a receiver, the receiver performance, therefore, is not optimized.